1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures, according to an SOI (silicon-on-insulator) technique.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently, and in the foreseeable future, the majority of integrated circuits are and will be based on silicon devices due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions at least at the area in the vicinity of the channel region, i.e., source and drain extension regions, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions. The requirement for shallow junctions having a high conductivity is commonly met by performing an ion implantation sequence to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and therefore one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a “blurring” of the dopant profile. A defined degree of blurring may be advantageous for defining critical transistor properties, such as the overlap between the extension regions and the gate electrode. In other areas of the drain and source regions, that is, in deeper lying portions, the diffusion may result in a reduction of the dopant concentration at the corresponding PN junction areas, thereby reducing the conductivity in the vicinity of these areas. Thus, on one hand, a high anneal temperature may be desirable in view of a high degree of dopant activation, re-crystallization of implantation-induced lattice damage and a desired diffusion at shallow areas of the extension regions, while, on the other hand, the duration of the anneal process should be short in order to restrict the degree of dopant diffusion in the deeper drain and source regions, which may reduce the dopant gradient at the respective PN junctions and also reduce the overall conductivity due to reducing the average dopant concentration. Therefore, for highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device, since the overall series resistance of the conductive path between the drain and source contacts may represent a dominant part for determining the transistor performance.
A further issue related to the lateral and vertical dopant profile of the drain and source regions and thus of the PN junctions may be presented by the overall capacitance of the PN junctions, which is roughly related to the effective interface formed by the PN junctions with respect to the remaining active region of the semiconductor device. In order to further enhance the performance of SOI transistors, the parasitic capacitance of the PN junctions may be significantly reduced by designing the vertical dopant profile in such a manner that a high dopant concentration is obtained that extends down to the buried insulating layer. In this way, only the laterally oriented interfaces of the PN junction of the drain and source regions contribute to the overall junction capacitance, while, additionally, the high dopant concentration extending down to the buried insulating layer provides the desired PN junction characteristics and also a reduced overall series resistance in the drain and source regions. However, providing deep drain and source regions with high dopant concentrations down to the buried insulating layer may require sophisticated implantation techniques, thereby contributing to the overall process complexity. In other cases, a moderately high dopant concentration at the buried insulating layer may be accomplished by adjusting the process parameters of the respective anneal processes in such a way that the diffusion of the dopants during the anneal process may result in the desired vertical dopant profile. The respective anneal parameters may, however, not be compatible with the requirement of a reduced transistor length, since a lateral diffusion, for instance in the extension regions, may also take place and result in a modified channel length, which may, therefore, require increased spacer widths to accommodate the increased diffusion activity during a respective anneal process. Thus, high temperature anneal processes with extended process times for inducing high diffusion activity and thus generating a high thermal budget may be a less attractive approach in view of increasing the packing density of sophisticated semiconductor devices. Consequently, the final performance of transistors in advanced SOI devices is a very complex combination of a plurality of factors, wherein the influence of many of these factors is difficult to be determined and wherein some of these factors may have a different effect on P-channel transistors and N-channel transistors.
Moreover, techniques have been recently developed in which the transistor performance, for instance the performance of P-channel transistors, may be significantly enhanced by providing a strained semiconductor material, such as a silicon/germanium compound, which may be formed in drain and source regions of silicon-based active transistor areas. The strained silicon/germanium compound, which may also be referred to as a silicon/germanium alloy, may be provided in a strained state due to a mismatch of the lattice spacing of natural silicon and natural silicon/germanium alloy. That is, the silicon/germanium material may be formed on the basis of the silicon lattice spacing, thereby resulting in a strained silicon/germanium crystal lattice, which may then interact with the neighboring semiconductor material to exert a stress and thus cause a certain strain. When providing the strained silicon/germanium alloy in the drain and source regions, the respective stress created by the strained material may act on the channel region of the transistor, thereby creating a respective compressive strain therein, which may enhance the charge carrier mobility. In highly scaled transistor devices based on the SOI architecture, significant benefits with respect to performance may be achieved by providing a highly strained semiconductor alloy in the vicinity of the channel region that extends along a significant portion in the depth direction in the semiconductor layer. Consequently, an efficient strain-inducing mechanism in SOI devices, in combination with a reduced parasitic junction capacitance, may result in an overall performance gain, while, additionally, a highly reduced thermal budget of the respective anneal processes may be desirable to provide the potential for reducing the lateral dimensions of the transistor devices, as explained above.
Upon a further device scaling, for instance according to the 45 nm MOSFET technology, the implant energy for forming the deep drain and source regions of SOI devices is substantially limited by the ion blocking capability of the gate electrode since the thickness of the semiconductor layer, and thus of the deep drain and source regions, is comparable to the height of the gate electrodes. Consequently, if a desired high dopant concentration is to be incorporated at a desired depth, for instance at the interface between the active semiconductor layer and the buried insulating layer in the SOI device, without using significant dopant diffusion, which may result in a reduced dopant concentration, as previously discussed, dopant species may also be incorporated in the channel region that is located below the gate electrode, thereby significantly deteriorating the transistor performance. In other words, if the implantation energy is selected moderately high so as to position the dopant species so as to extend to the buried insulating layer high concentration, thereby reducing the junction capacitance, the polysilicon gate electrode may not efficiently block the implantation species, thereby resulting in a non-desired degree of doping of the channel region. As a consequence, the resulting transistor performance is significantly affected by a plurality of interrelated factors, such as the thickness of the active semiconductor layer, the height of the gate electrodes, the lateral and vertical dopant profiles in the corresponding active regions of the transistor elements, the resulting dopant gradients at the PN junction, the effective overall size and shape of the PN junction and the like. Since the variation of one or more of these factors may involve a plurality of interrelated modifications of processes and components of the individual semiconductor devices, it is extremely difficult to introduce performance enhancing techniques that may result in a significant overall performance gain. For example, a plurality of performance enhancing mechanisms may be provided that may be targeted to enhance performance of one type of circuit element, such as N-channel transistors or P-channel transistors, without significantly negatively affecting the other type of circuit element, thereby contributing to an overall increase of performance of a complex SOI device including complementary transistors. For instance, one efficient technique for enhancing performance of P-channel transistors without significantly affecting the behavior of N-channel transistors is the provision of a compressive strain-inducing semiconductor alloy, as described above. On the other hand, a plurality of mechanisms, for instance with respect to the overall device geometry of P-channel transistors and N-channel transistors, may have a different influence on the total performance of an SOI device, in particular for sophisticated technology standards.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.